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r07ds0674ej0101 rev.1.01 page 1 of 10 aug 19, 2013 preliminary data sheet pa2373t1p dual (drain common), n- channel mosfet 24v, 6a, 23.0m description the pa2373t1p is a switching device, which can be driven directly by a 2.5 v power source. the pa2373t1p features a low on- state resistance and excellent switching characteristics, and is suitable for applications such as power switch of portable machine and so on. best su ite for single cell lib application. features ? 2.5 v drive available ? low on-state resistance ? r ss(on)1 = 23.0 m max. (v gs = 4.5 v, i s = 3.0 a) ? r ss(on)2 = 24.0 m max. (v gs = 4.0 v, i s = 3.0 a) ? r ss(on)3 = 25.0 m max. (v gs = 3.8 v, i s = 3.0 a) ? r ss(on)4 = 30.0 m max. (v gs = 3.1 v, i s = 3.0 a) ? r ss(on)4 = 39.0 m max. (v gs = 2.5 v, i s = 3.0 a) ? built-in g-s protection diode against esd ordering information part no. lead plating packing package pa2373t1p-e4-a ? 1 ni/au reel 5000 p/reel 4-pin eflip-lga note: ? 1. pb-free (this product does not contain pb in the external electrode and other parts.) absolute maximum ratings (t a = 25 c) item symbol ratings unit source to source voltage (v gs = 0 v) v sss 24.0 v gate to source voltage (v ds = 0 v) v gss 12.0 v source current (dc) ? 1 i s(dc) 6.0 a source current (pulse) ? 2 i s(pulse) 60 a total power dissipation (2 units) ? 1 p t1 1.3 w channel temperature t ch 150 c storage temperature t stg ? 55 to + 150 c note: ? 1. mounted on ceramic board of 50 cm 2 1.0 mmt ? 2. pw 10 s, duty cycle 1% r07ds0674ej0101 rev.1.01 aug 19, 2013
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 2 of 10 aug 19, 2013 electrical characteristics (t a = 25 c) characteristics symbol min. typ. max. unit test conditions zero gate voltage source current i sss 1 a v ss = 24 v, v gs = 0 v, test circuit 1 gate leakage current i gss 10 a v gs = 12 v, v ss = 0 v, test circuit 2 gate to source cut-off voltage v gs(off) 0.5 0.9 1.5 v v ss = 10 v, i s = 1.0 ma, test circuit 3 forward transfer admittance ? ? 1 r ss(on)1 14 19 23 m v gs = 4.5 v, i s = 3.0 a, test circuit 5 r ss(on)2 14.4 20 24 m v gs = 4.0 v, i s = 3.0 a, test circuit 5 r ss(on)3 14.6 20.5 25 m v gs = 3.8 v, i s = 3.0 a, test circuit 5 r ss(on)4 16 23 30 m v gs = 3.1 v, i s = 3.0 a, test circuit 5 r ss(on)5 19 27 39 m v gs = 2.5 v, i s = 3.0 a, test circuit 5 input capacitance c iss 1230 pf v ss = 10 v, output capacitance c oss 370 pf v gs = 0 v, reverse transfer capacitance c rss 282 pf f = 1.0 mhz, test circuit 7 turn-on delay time t d(on) 6.2 s v dd = 20 v, i s = 6.0 a, rise time t r 36 s v gs = 4.0 v, turn-off delay time t d(off) 37 s r g = 6.0 , fall time t f 61 s test circuit 8 total gate charge q g 22 nc v dd = 19.2 v, v g1s1 = 4.0 v, i s = 6.0 a, test circuit 9 body diode forward voltage ? 1 v f(s-s) 0.9 v i f = 6.0 a, v gs = 0 v, test circuit 6 note: ? 1. pulsed test both the fet1 and the fet2 are measured. test ci rcuits are example of measuring the fet1 side. test circuit 1 i sss test circuit 2 i gss g2 s2 s1 v ss g1 a when fet1 is measured, between gate and source of fet2 are shorted. g1 s1 v gs a g2 g1 s2 s1 a g2 test circuit 3 v gs ( off ) test circuit 4 | y fs | when fet1 is measured, between gate and source of fet2 are shorted. g1 s2 s1 v gs g2 v ss a g1 s2 s1 g2 a i s / v gs g1 s2 s1 v gs g2 v ss a g1 s2 s1 g2 a
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 3 of 10 aug 19, 2013 test circuit 5 r ss ( on ) test circuit 6 v f ( s-s ) v ss /i s g1 s2 s1 v gs g2 v i s g1 s2 s1 g2 v v ss when fet1 is measured, fet2 is added v gs + 4.5 v. g1 s1 v gs = 0 v g2 v i f 4.5 v g1 s1 s2 g2 v v ss test circuit 7 c iss c oss c rss g1 s2 s1 g2 v ss capacitance bridge g1 s1 g2 capacitance bridge g1 s2 s1 g2 v ss capacitance bridge g1 s2 s1 g2 capacitance bridge g1 s2 s1 g2 v ss capacitance bridge g1 s2 s1 g2 capacitance bridge test circuit 8 t d ( on ) , t r , t d ( off ) , t f g1 s2 s1 r g g2 v r l v dd pg. v 0 v gs = 1 s duty cycle 1% v gs wave form v ss wave form v gs 10% 90% v gs 10% 0 v ss 90% 90% t d(on) t r t d(off) t f 10% v ss 0 t on t off test circuit 9 q g g1 s2 s1 i g = 2 ma g2 a r l v dd pg. 50 a pg.
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 4 of 10 aug 19, 2013 derating factor of forward bias safe operating area total power dissipation vs. ambient temperature dt - percentage of rated power - % 0 20 40 60 80 100 120 0 25 50 75 100 125 150 175 t a - ambient temperature - c p t - total power dissipation - w 0 0.4 0.8 1.2 1.6 0 25 50 75 100 125 150 175 mounted on ceramic board of 50 cm 2 x 1.0 mmt t a - ambient temperature - c forward bias safe operating area i s - drain current - a 0.01 0.1 1 10 100 0.01 0.1 1 10 100 dc single pulse p(fet1):p(fet2) = 1:1 mounted on ceramic board of 50 cm 2 1.0 mmt i s(dc) r ss(on) limited (v gs = 4.5 v) v ss - drain to source voltage - v transient thermal resistance vs. pulse width r th(t) - transient thermal resistance - c/w 0.1 1 10 100 1000 mounted on bt resin board of 40.5 x 25 x 1.5 mmt single pulse p(fet1):p(fet2) = 1:1 mounted on ceramic board of 50 cm 2 1.0 mmt pw - pulse width - s 100 1 m 10 m 100 m 1 10 100 1000
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 5 of 10 aug 19, 2013 source current vs. source to source voltage forward transf er characteristics i s - source current - a 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 4.0 v v gs = 4.5 v 3.1 v 2.5 v test circuit 5 pulsed v ss - source to source voltage - v i s - source current - a 0.001 0.01 0.1 1 10 0 0.5 1 1.5 2 2.5 test circuit 3 v ss = 10 v pulsed t a = 125c 75c 25c ? 25c v gs - gate to source voltage - v gate to source cut-off voltage vs. channel temperature forward transfer admittance vs. source current v gs(off) - gate to source cut-off voltage - v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 50 100 150 test circuit 3 v ss = 10 v i s = 1.0 ma t ch - channel temperature - c | y fs | - forward transfer admittance - s 0.1 1 10 100 0.01 0.1 1 10 test circuit 4 v ss = 5 v pulsed t a = 125c 75c 25c ? 25c i s - source current - a source to source on-state resistance vs. source current source to source on-state resistance vs. gate to source voltage r ss(on) - source to source on-state resistance - m 0 10 20 30 40 50 60 70 0.01 0.1 1 10 100 test circuit 5 pulsed 4.0 v v gs = 2.5 v 4.5 v 3.1 v i s - source current - a r ss(on) - source to source on-state resistance - m 0 5 10 15 20 25 30 35 40 0246810 test circuit 5 i s = 3.0 a pulsed v gs - gate to source voltage - v
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 6 of 10 aug 19, 2013 source to source on-state resistance vs. channel temperature capacitance vs. source to source voltage r ss(on) - source to source on-state resistance - m 0 10 20 30 40 50 -50 0 50 100 150 v gs = 2.5 v 3.1 v test circuit5 i s = 3.0 a pulsed 4.0 v 4.5 v t ch - channel temperature - c c iss , c oss , c rss - capacitance - pf 10 100 1000 10000 0.1 1 10 100 test circuit 7 v gs = 0 v f = 1.0 mhz c rss c iss c oss v ss - source to source voltage - v switching characteristics dynamic input characteristics t d(on) , t r , t d(off) , t f - switching time - s 1 10 100 1000 0.1 1 10 test circuit 8 v dd = 20 v v gs = 4.0 v rg = 6.0 t d(on) t r t d(off) t f i s - source current - a v gs - gate to source voltage - v 0 1 2 3 4 0 5 10 15 20 25 test circuit 9 i s = 6 a v dd = 4.8 v 12 v 19.2 v q g - gate charge - nc v gs - gate to source voltage - v source to source diode forward voltage i f - diode forward current - a 0.01 0.1 1 10 100 0 0.5 1 1.5 2 v gs = 2.5 v 0 v test circuit 6 pulsed v f(s-s) - source to source voltage - v
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 7 of 10 aug 19, 2013 example of application circuit li-ion battery (1 cell) protection circuit battery protection ic p+ p ? lithium- ion battery cell protection circuit lithium-ion battery pack pa2373t1p
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 8 of 10 aug 19, 2013 package drawings (unit: mm) 4-pin eflip-lga g1 s2 g2 s1 1.62 0.05 0.2 0.05 1.62 0.05 s1: source 1 g1: gate 1 g2: gate 2 s2: source 2 0.65 0.65 4 - 0.3 dot area (for in-house) 1-pin index mark s1 top view bottom view equivalent circuit fet1 gate1 fet2 gate2 body diode protection diode source2 source1 gate remark the diode connected between the gate and source of the transistor serves as a protector against esd. when this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. renesas package code : sxlg0004jb-a
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 9 of 10 aug 19, 2013 usage cautions when you use this device, in order to prevent a customer?s hazard and damage , use it with understanding the following contents. if used exceeding recommended conditions, there is a possibility of causing the device and characteristic degradation. 1. this device is very thin device and should be handled with caution for mechanical stress. the distortion applied to the device should become below 2000 10 -6 . if the distortion exceeds 2000 10 -6 , the characteristic of a device may be degraded and it may result in failure. 2. please do not damage the device when you handle it. the use of metallic tw eezers has the possibility of giving the wound. mounting with the nozzle w ith clean point is recommended. 3. when you mount the device on a subs trate, carry out within our recomme nded soldering conditions of infrared reflow. if mounted exceeding the conditions , the characteristic of a device may be degraded and it may result failure. 4. when you wash the device mounted the board, carry out within our reco mmended conditions. if washed exceeding the conditions, the characteristic of a device ma y be degraded and it may result in failure. 5. when you use ultrasonic wave to substrate after the device mounting, prevent from touching a resonance directly. if it touches, the characteristic of a device ma y be degraded and it may result in failure. 6. only the epoxy resin of the semiconductor grade is recommended as coating material. 7. please refer to figure 2 as an exam ple of the mounting pad. optimize the land pattern in consideration of density, appearance of solder fillets, common difference, etc in an actual design. 8. the marking side of this device is an internal electrode. please neither contact with terminals of other parts nor take out the electrode. figure 1 recommended soldering conditions of infrared reflow 260?c max. 220?c to 60 s 160?c 180?c (main heating) to 10 s 60 to 120 s (preheating) time(s) infrared reflow temperature profile maximum temperature (package's surface temperature) : 260?c or below time at maximum temperature : 10 s or less time of temperature higher than 220?c : 60 s or less preheating time at 160 to 180?c : 60 to 120 s maximum number of reflow processes : 3 times maximum chlorine content of rosin flux (mass percentage) : 0.2% or less package's surface temperature (?c)
pa2373t1p chapter title r07ds0674ej0101 rev.1.01 page 10 of 10 aug 19, 2013 figure 2 the example of the mounting pad (unit : mm) 0.65 0.65 4 - 0.30 figure 3 the unit orientation reel side leader side top view s2 g1 s1 g2 s2 g1 s1 g2
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